D K 2 2 7 A - 5 0 HITACHI Native| Translation ------+-----+-----+----- Form 2.5"/SUPERSLIMLINE Cylinders | | | Capacity form/unform 5000/ MB Heads | | | Seek time / track 12.0/ ms Sector/track | | | Controller IDE / ATA3 ULTRA Precompensation Cache/Buffer 512 KB Landing Zone Data transfer rate MB/S int Bytes/Sector 512 33.000 MB/S ext UDMA Recording method operating | non-operating -------------+-------------- Supply voltage Temperature *C | Power: sleep W Humidity % | standby W Altitude km | idle W Shock g | 500 seek W Rotation RPM read/write W Acoustic dBA spin-up W ECC Bit MTBF h Warranty Month Lift/Lock/Park YES Certificates ********************************************************************** L A Y O U T ********************************************************************** HITACHI DK227A SPECIFICATIONS REV. 1, K6601560 97/11/08 ----+---------------------------------------------------+-PCB- | B D 2 4 o o o o o o o o o o o o o o o o o o o 44| | A C 1 3 o o o o o o o o o o o o o o o o o o o 43| +---------------------------------------------------+ ********************************************************************** J U M P E R S ********************************************************************** HITACHI DK227A SPECIFICATIONS REV. 1 K6601560 97/11/08 Jumper Setting ============== Master/Slave Setting -------------------- When the drive is connected to the host bus, Master/Slave setting is necessary to configure a drive as a master (0) or a slave (1). Master/Slave setting is established between drives on the interface connector by using jumper 0-2 (pin# A, B, D). The master drive is assigned to drive address 0, the slave drive is assigned to drive address 1. (1) Master (or single) +43-------------------1---C-A-+ | o o ----------- o o o o o | If all of pin# A, B, D are open, | o o ----------- o o o o o | the drive is a master (or single). -+44-------------------2---D-B-+--- (2) Slave +43-------------------1---C-A-+ | o o ----------- o o o o X | If Jumper Position A-B is used, | o o ----------- o o o o X | the drive is slave (1). +44-------------------2---D-B-+ (3) CSEL Selection +43-------------------1---C-A-+ | o o ----------- o o o o o | If Jumper Position B-D is used, | o o ----------- o o o xxx | Master/Slave setting is determinated +44-------------------2---D-B-+ by the condition of CSEL signal (pin# 28). Connector Pin Assignments ------------------------- Pin | Function | Pin | Function -----+----------------+------+----------- A | JUMPER 1 | B | JUMPER 0 -----+----------------+------+----------- C | RESERVED | D | JUMPER 2 -----+----------------+------+----------- E | KEY (REMOVED) | F | KEY (REMOVED) -----+----------------+------+----------- 1 | RESET- | 2 | GND -----+----------------+------+----------- 3 | DD7 | 4 | DD8 -----+----------------+------+----------- 5 | DD6 | 6 | DD9 -----+----------------+------+----------- 7 | DD5 | 8 | DD10 -----+----------------+------+----------- 9 | DD4 | 10 | DD11 -----+----------------+------+----------- 11 | DD3 | 12 | DD12 -----+----------------+------+----------- 13 | DD2 | 14 | DD13 -----+----------------+------+----------- 15 | DD1 | 16 | DD14 -----+----------------+------+----------- 17 | DD0 | 18 | DD15 -----+----------------+------+----------- 19 | GND | 20 | KEY (REMOVED) -----+----------------+------+----------- 21 | DMARQ | 22 | GND -----+----------------+------+----------- 23 | DIOW- | 24 | GND -----+----------------+------+----------- 25 | DIOR- | 26 | GND -----+----------------+------+----------- 27 | IORDY | 28 | CSEL -----+----------------+------+----------- 29 | DMACK- | 30 | GND -----+----------------+------+----------- 31 | INTRQ | 32 | IOCS16- -----+----------------+------+----------- 33 | DA1 | 34 | PDIAG- -----+----------------+------+----------- 35 | DA0 | 36 | DA2 -----+----------------+------+----------- 37 | CS1FX- | 38 | CS3FX -----+----------------+------+----------- 39 | DASP- | 40 | GND (MOTOR) -----+----------------+------+----------- 41 | 5VDC (LOGIC) | 42 | 5VDC (MOTOR) -----+----------------+------+----------- 43 | GND (LOGIC) | 44 | RESERVED -----+----------------+------+----------- Description of the Interface Signals ------------------------------------ The interface is an ATA (IDE) interface. Reserved pins should be left unconnected. The following table shows the signal definitions. "I" of I/O type represents an input signal for the drive and "O" represents an input signal from the drive. +------------+-----+--------+---------------------------------------+ |Signal name | Pin |I/O type| Description | |RESET- | 1 | I | This is a reset signal output from the| | | | | host system and to be used for inter- | | | | | face logical circuit. | +------------+-----+--------+---------------------------------------+ |DD0-DD15 | 3-18| I/O | This is a 16 bit directional bus. The | | | | | lower 8 bits are used for register | | | | | access other than data register. | +------------+-----+--------+---------------------------------------+ |DIOW- | 23 | I | The rising edge of this Write Strobe | | | | | signal enables data from a register on| | | | | the drive. | +------------+-----+--------+---------------------------------------+ |DIOR- | 25 | I | Activating this Read Strobe signal | | | | | enables data from a register on the | | | | | drive to be clocked onto the host data| | | | | bus. The rising edge of this signal | | | | | latches data at the host. | +------------+-----+--------+---------------------------------------+ |IORDY | 27 | O | This signal is used to temporarily | | | | | stop the host register access (read or| | | | | write) when the drive is not ready to | | | | | respond to a data transfer request. | +------------+ | +---------------------------------------+ |DDMARDY- * | | | This signal is a flow control signal | | | | | for Ultra DMA data out burst. Drive | | | | | asserts this signal, and indicates | | | | | that the drive is ready to receive | | | | | Ultra DMA data out burst. | +------------+ | +---------------------------------------+ |DSTROBE * | | | This signal is the data in strobe | | | | | signal from the drive for an Ultra | | | | | DMA data in burst. Both the rising and| | | | | falling edge latch the data from DD | | | | | (15:0) into the host. | +------------+-----+--------+---------------------------------------+ |CSEL | 28 | I | This signal is used to configure a | | | | | drive as either Drive 0 or 1 when CSEL| | | | | mode is selected. This signal is | | | | | pulled up inside the drive. | | | | | +-----+--------------+ | | | | | |CSEL |Drive address | | | | | | +-----+--------------+ | | | | | |GND | 0 | | | | | | +-----+--------------+ | | | | | |OPEN | 1 | | | | | | +-----+--------------+ | +------------+-----+--------+---------------------------------------+ |INTRQ | 31 | O | This is an interruption signal for the| | | | | host system. This signal is asserted | | | | | by a selected drive when the nIEN bit | | | | | in the Device Control Register is "0".| | | | | In other cases, this signal should be | | | | | a high impedance state. | +------------+-----+--------+---------------------------------------+ |IOCS16- | 32 | O | This signal indicates to the host that| | | | | the 16 bis data port has been | | | | | addressed an a 16 bit word can be read| | | | | or written to the drive. | +------------+-----+--------+---------------------------------------+ |DA0-2 |33,35| I | This is a register address signal from| | | 36 | | the host system. | +------------+-----+--------+---------------------------------------+ |PDIAG- | 34 | I/O | This signal is asserted by Drive 1 to | | | | | indicate to Drive 0 that it has | | | | | completed diagnostics. This signal is | | | | | pulled up inside the drive. | +------------+-----+--------+---------------------------------------+ |CS1FX- | 37 | I | This drive chip selection signal is | | | | | used to select the Command Block | | | | | Registers from the host system. | +------------+-----+--------+---------------------------------------+ |CS3FX- | 38 | I | This drive chip selection signal is | | | | | used to select the Control Block | | | | | Registers from the host system. | +------------+-----+--------+---------------------------------------+ |DASP- | 39 | I/O | This signal indicates that a drive is | | | | | active or that Drive 1 is present | | | | | when power is turned on. | +------------+-----+--------+---------------------------------------+ |DMARQ | 21 | O | This signal, used for DMA data | | | | | transfers between host and drive, | | | | | shall be asserted by the drive when | | | | | it is ready to transfer data. | +------------+-----+--------+---------------------------------------+ |DMACK- | 29 | I | This signal shall be used by the host | | | | | in reponse to DMARQ to either | | | | | acknowledge that data has been | | | | | accepted, or that data is available. | +------------+-----+--------+---------------------------------------+ * Signal Name in Ultra DMA mode ********************************************************************** I N S T A L L ********************************************************************** HITACHI DK227A SPECIFICATIONS REV. 1 K6601560 97/11/08 Notes On Installation ===================== Installation direction ---------------------- horizontally vertically +-----------------+ +--+ +--+ | | | +-----+ +-----+ | | | | | | | | | +-+-----------------+-+ | | | | | | +---------------------+ | | | | | | | | | | | | | | | | | | +---------------------+ | +-----+ +-----+ | +-+-----------------+-+ +--+ +--+ | | | | +-----------------+ The drive will operate in all axis (6 directions). Screws: M3 (3.5mm) Connector --------- This device has 2mm pitch interface connector which contains a power line. The connector part list is shown in the following table. +--------------------+-----------------+----------------------+ |Interface cable side| Signal Connector| molex 87259-4413 | | | Receptacle | or equivalent | | +-----------------+----------------------+ | | Cable | AWG#28 or equivalent | +--------------------+-----------------+----------------------+ |Drive side | Signal Connector| molex 87400-5005 or | | | Plug | equivalent | +--------------------+-----------------+----------------------+ The I/O signal levels are as follows: Input signal High level +2.0V Vcc+0.5V Low level -0.5V 0.8V Output signal High level +2.4V +5.25V or an open circuit Low level +0.4V or less (IOL=2mA) +0.5V or less (IOL=24mA) The I/F cable should be no longer than 50cm (20 inches) include the circuit pattern length in the host system. Recommended type of jumper socket: Vendor: Kyocera Elco Corporation Part Number: 20-8387-002-005-801 ********************************************************************** F E A T U R E S ********************************************************************** HITACHI DK227A SPECIFICATIONS K6601560 REV. 1, 97/11/08 Introduction ------------ The DK227A series disk drive embodies large capacity such as 4090MB (12.7 mm height) in a small form factor (2.5 inch) by applying the latest high-density record technology. The drives are high performances and can operate at 12 ms of average seek times and transfer data up to 16.6 MB/s in PIO mode 4 and DMA mode 2, and 33.3MB/s in Ultra DMA mode 2. The high reliability (MTTF of 300,000 hours) is achieved by a reduction in number of parts and tight controls on quality. The power consumption of the 2.5 inch DK227A series drives is drastically reduced over similar capacity 3.5" disk drives. The drives support a standard ATA-3 (IDE) interface. Execute drive diagnostic [90h] ------------------------------ This command allows the drive to perform a self-diagnostic. When DRV0 and DRV1 are connected in the daisy chain mode, this command is executed for both of the drives. When the drive receives this command, it sets BSY=1 and executes the selfdiagnostic operation. Then the drive registers the diagnostic result in the Error register, clears BSY, and generates an interrupt. Code | Contents ------+-------------------- 01 | No Error ------+-------------------- 02 | Controller error ------+-------------------- 03 | Sector buffer error ------+-------------------- 05 | CPU error ------+-------------------- 8x | DRV1 error Handling -------- It is necessary to prevent vibration, shock, and static electricity to the because it will damage the precision parts. In particular, prevent vibration or shock generated by dropping, knocking over, or hitting the drive. Also, avoid touching the electrical components directly, which can discharge electrostatic eneregy and damage the drive.